SH7672 datasheet(205/1292 Pages) RENESAS

205 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 179 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

HIZCNT*

R/W

High-Z Control

Specifies the state of CKE,

RAS, and CAS in software

standby mode.

0: High impedance in software standby mode

1: Driven in software standby mode

Note:

For High-Z control of CKIO, see section 9, Clock Pulse Generator (CPG).

7.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0, 3 to 6)

CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number

of idle cycles between bus cycles, and the bus width.

Do not access external memory other than area 0 until CSnBCR initial setting is completed.

Idle cycles may be inserted even when they are not specified. For details, see section 7.5.8, Wait

between Access Cycles.

0011011011011011

R/W

00000

000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

Note:

CSnBCR samples the external pin (MD) that specify the bus width at power-on reset.

IWW[2:0]

IWRWD[2:0]

IWRWS[2:0]

IWRRD[2:0]

IWRRS[2:0]

TYPE[2:0]

ENDIAN

BSZ[1:0]

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

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