SH7672 datasheet(203/1292 Pages) RENESAS

203 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 177 of 1262

REJ09B0437-0100

7.4.1

Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

987654321

0000000000000000

RRRRRRRRRRRRRRRR

0001000000010000

RRRRRRR

R/W

RRR

R/W









DMAIW[2:0]

DMA

IWA



HIZ

MEM

HIZ

CNT

Bit

Bit Name

Initial

Value

R/W

Description

31 to 13



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.



Reserved

This bit is always read as 1. The write value should

always be 1.

11 to 9



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

8 to 6

DMAIW[2:0]

000

R/W

Wait states between access cycles when DMA single

address transfer is performed.

Specify the number of idle cycles to be inserted after

an access to an external device with DACK when DMA

single address transfer is performed. The method of

inserting idle cycles depends on the contents of

DMAIWA.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

100: 6 idle cycles inserted

101: 8 idle cycles inserted

110: 10 idle cycles inserted

111: 12 idle cycles inserted

SH7672 Datasheet(PDF) 203 Page - Renesas Technology Corp

SH7672 Datasheet(HTML) 203 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL