SH7672 datasheet(200/1292 Pages) RENESAS

200 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 174 of 1262

REJ09B0437-0100

7.3

Area Overview

7.3.1

Address Map

In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled,

cache-disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved

areas) according to the upper bits of the address.

External address spaces CS0, CS3 to CS6 are cache-enabled when internal address A29 = 0 or

cache-disabled when A29 = 1.

The kind of memory to be connected and the data bus width are specified in each partial space.

The address map for the external address space is listed below.

Table 7.2

Address Map

Internal Address

Space

Memory to be Connected

Cache

H'00000000 to H'03FFFFFF

CS0

Normal space, SRAM with byte selection

H'04000000 to H'07FFFFFF

Other

Reserved area

H'08000000 to H'0BFFFFFF

Other

Reserved area

H'0C000000 to H'0FFFFFFF CS3

Normal space, SRAM with byte selection, SDRAM

H'10000000 to H'13FFFFFF

CS4

Normal space, SRAM with byte selection

H'14000000 to H'17FFFFFF

CS5

Normal space, SRAM with byte selection, PCMCIA

H'18000000 to H'1BFFFFFF

CS6

Normal space, SRAM with byte selection, PCMCIA

H'1C000000 to H'1FFFFFFF Other

Reserved area

Cache-enabled

H'20000000 to H'23FFFFFF

CS0

Normal space, SRAM with byte selection,

burst ROM (asynchronous or synchronous)

H'24000000 to H'27FFFFFF

Other

Reserved area

H'28000000 to H'2BFFFFFF

Other

Reserved area

H'2C000000 to H'2FFFFFFF CS3

Normal space, SRAM with byte selection, SDRAM

H'30000000 to H'33FFFFFF

CS4

Normal space, SRAM with byte selection

H'34000000 to H'37FFFFFF

CS5

Normal space, SRAM with byte selection, PCMCIA

H'38000000 to H'3BFFFFFF

CS6

Normal space, SRAM with byte selection, PCMCIA

H'3C000000 to H'3FFFFFFF Other

Reserved area

Cache-disabled

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