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SH7672 Datasheet(PDF) 197 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 197 Page - Renesas Technology Corp |
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197 / 1292 page ![]() Section 7 Bus State Controller (BSC) Rev. 1.00 Nov. 14, 2007 Page 171 of 1262 REJ09B0437-0100 Figure 7.1 shows a block diagram of the BSC. CMNCR CS0WCR CS7WCR CS0BCR CS7BCR SDCR RTCSR RTCNT RTCOR Comparator Bus mastership controller Wait controller Area controller Memory controller Refresh controller [Legend] BSC CS0 to CS7 REFOUT WAIT MD A25 to A0, D31 to D0 BACK BREQ BS, RD/WR, RD, WE3 to WE0, RASU, RASL, CASU, CASL CKE, DQMxx, AH, FRAME, IOIS16, CE2A, CE2B CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0 to 7) CSn space bus control register (n = 0 to 7) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Figure 7.1 Block Diagram of BSC |
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