SH7672 datasheet(195/1292 Pages) RENESAS

195 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 169 of 1262

REJ09B0437-0100

Section 7

Bus State Controller (BSC)

The bus state controller (BSC) outputs control signals for various types of memory and external

devices that are connected to the external address space. BSC functions enable this LSI to connect

directly with SRAM, SDRAM, and other memory storage devices, and external devices.

7.1

Features

1. External address space

 A maximum of 64 Mbytes for each of areas CS0 and CS3 to CS6.

 Can specify the normal space interface, SRAM interface with byte selection, SDRAM, and

PCMCIA interface for each address space.

 Can select the data bus width (8, 16, or 32 bits) for each address space.

 Controls insertion of wait cycles for each address space.

 Controls insertion of wait cycles for each read access and write access.

 Can set independent idle cycles during the continuous access for five cases: read-write (in

same space/different spaces), read-read (in same space/different spaces), the first cycle is a

write access.

2. Normal space interface

 Supports the interface that can directly connect to the SRAM.

3. SDRAM interface

 Can set the SDRAM in up to two areas.

 Multiplex output for row address/column address.

 Efficient access by single read/single write.

 High-speed access in bank-active mode.

 Supports an auto-refresh and self-refresh.

 Supports power-down modes.

 Issues MRS and EMRS commands.

4. PCMCIA direct interface

 Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver.

4.2 (PCMCIA2.1 Rev. 2.1).

 Wait-cycle insertion controllable by program.

5. SRAM interface with byte selection

 Can connect directly to a SRAM with byte selection.

SH7672 Datasheet(PDF) 195 Page - Renesas Technology Corp