SH7672 datasheet(243/1292 Pages) RENESAS

243 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 217 of 1262

REJ09B0437-0100

7.5

Operation

7.5.1

Endian/Access Size and Data Alignment

This LSI supports both big endian, in which the most significant byte (MSB) of data is that in the

direction of the 0th address, and little endian, in which the least significant byte (LSB) is that in

the direction of the 0th address. In the initial state after a power-on reset, all areas will be in big

endian mode. Little endian cannot be selected for area 0. However, the endian of areas 3 to 6 can

be changed by the setting in the CSnBCR register setting as long as the target space is not being

accessed.

Three data bus widths (8 bits, 16 bits, and 32 bits) are selectable for areas 3 to 6, allowing the

connection of normal memory and of SRAM with byte selection. Two data bus widths (16 bits and

32 bits) are available for SDRAM. Two data bus widths (8 bits and 16 bits) are available for the

PCMCIA interface. For MPX-I/O, the data bus width can be fixed to either 8 or 16 bits, or made

selectable as 8 bits or 16 bits by one of the address lines. Data alignment is in accord with the data

bus width selected for the device. This also means that four read operations are required to read

longword data from a byte-width device. In this LSI, data alignment and conversion of data length

is performed automatically between the respective interfaces. The data bus width of area 0 is fixed

to 8 bits or 16 bits by the MD_BW pin setting at a power-on reset.

Tables 7.5 to 7.10 show the relationship between device data width and access unit. Note that the

correspondence between addresses and strobe signals for the 32- and 16-bit bus widths depends on

the endian setting. For example, with big endian and a 32-bit bus width,

WE3 corresponds to the

0th address, which is represented by

WE0 when little endian has been selected. Little endian

cannot be selected for area 0. Note also that 32-bit and 16-bit accesses coincide in instruction

fetching, therefore, it is difficult to allocate instruction to little endian area. Make sure to execute

instruction in big endian area.

SH7672 Datasheet(PDF) 243 Page - Renesas Technology Corp