SH7672 datasheet(241/1292 Pages) RENESAS

241 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 215 of 1262

REJ09B0437-0100

7.4.11

Internal Bus Master Bus Priority Register (IBMPR)

IBMPR is a 32-bit register that sets the bus priority for the internal bus masters excluding the

CPU.

If internal bus masters excluding the same CPU are set at different priority levels, the highest one

will be effective. After an attempt to set internal bus masters in an overlapping manner, if some of

them failed to be set, then these failing bus masters will not be able to acquire bus mastership.

Rewriting this register while any of the A-DMAC (including F-DMAC), E-DMAC, and DMAC is

operating is prohibited. When rewriting this register, make sure that none of the A-DMAC

(including F-DMAC), E-DMAC, and DMAC is not started.

For details, see section 7.5.9 (2), Access from the Side of the LSI Internal Bus Master.

Bit:

Initial Value

R/W:

Bit:

Initial Value

R/W:

0001001000110000

R/W

00000000

RRRRRRRR

00000000

RRRRRRRR



0P1R[1:0]



0P2R[1:0]



0P3R[1:0]





Bit

Bit Name

Initial

Value

R/W

Description

31, 30



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

29, 28

0P1R[1:0]

R/W

Of the internal bus masters excluding the CPU (that is,

A-DMAC (including F-DMAC), E-DMAC, and DMAC),

set the internal bus master having the highest priority

level.

00: No setting

01: A-DMAC (including F-DMAC)

10: E-DMAC

11: DMAC

SH7672 Datasheet(PDF) 241 Page - Renesas Technology Corp

SH7672 Datasheet(HTML) 241 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL