SH7672 datasheet(288/1292 Pages) RENESAS

288 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 262 of 1262

REJ09B0437-0100

(8)

Refreshing

This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by

clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can

be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long

period, self-refresh mode, in which the power consumption for data retention is low, can be

activated by setting both the RMODE bit and the RFSH bit to 1.

(a)

Auto-refreshing

Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0

in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should

be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings

for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0

and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts

counting up from the value at that time. The RTCNT value is constantly compared with the

RTCOR value, and if the two values are the same, a refresh request is generated and an auto-

refresh is performed for the number of times specified by the RRC2 to RRC0. At the same time,

RTCNT is cleared to zero and the count-up is restarted.

Figure 7.25 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL

command is issued in the Tp cycle to make all the banks to pre-charged state from active state

when some bank is being pre-charged. Then REF command is issued in the Trr cycle after

inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A

new command is not issued for the duration of the number of cycles specified by the WTRC1 and

WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to

satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the

Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is

longer than or equal to 1 cycle.

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