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SH7672 Datasheet(PDF) 291 Page - Renesas Technology Corp

Part # SH7672
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series
PDF  1292 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7672 Datasheet(HTML) 291 Page - Renesas Technology Corp

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Section 7
Bus State Controller (BSC)
Rev. 1.00 Nov. 14, 2007 Page 265 of 1262
REJ09B0437-0100
Tpw
Tp
Trr
Trc
Trc
Hi-z
Trc
CKIO
CKE
A25 to A0
CSn
RD/
WR
RAS
DQMxx
D31 to D0
BS
DACKn*2
A12/A11*1
CAS
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 7.26
Self-Refresh Timing
(9)
Relationship between Refresh Requests and Bus Cycles
If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle
to be completed.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval must be
prevented from occurring.



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