SH7672 datasheet(295/1292 Pages) RENESAS

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Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 269 of 1262

REJ09B0437-0100

(12) Low-Power SDRAM

The low-power SDRAM can be accessed using the same protocol as the normal SDRAM.

The differences between the low-power SDRAM and normal SDRAM are that partial refresh

takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh

function, and that power consumption is low during refresh under user conditions such as the

operating temperature. The partial refresh is effective in systems in which there is data in a work

area other than the specific area can be lost without severe repercussions.

The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode

registers as the normal SDRAM. This LSI supports issuing of the EMRS command.

The EMRS command is issued according to the conditions specified in table below. For example,

if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued

to the CS3 space in the following sequence: PALL -> REF

× 8 -> MRS -> EMRS. In this case, the

MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data

H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the

CS3 space in the following sequence: PALL -> MRS -> EMRS.

Table 7.19

Output Addresses when EMRS Command Is Issued

Command to be

Issued

Access

Address

Access Data

Write

Access

Size

MRS

Command

Issue Address

EMRS

Command

Issue Address

CS3 MRS

H'FFFC5XX0

H'********

16 bits

H'0000XX0



CS3 MRS + EMRS

(with refresh)

H'FFFC5XX0

H'0YYYYYYY 32 bits

H'0000XX0

H'YYYYYYY

CS3 MRS + EMRS

(without refresh)

H'FFFC5XX0

H'1YYYYYYY 32 bits

H'0000XX0

H'YYYYYYY

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