SH7672 datasheet(293/1292 Pages) RENESAS

293 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 267 of 1262

REJ09B0437-0100

(11) Power-On Sequence

In order to use SDRAM, mode setting must first be made for SDRAM after waiting for 100

µs or

a longer period after powering on. This 100-

µs or longer period should be obtained by a power-on

reset generating circuit or software.

To perform SDRAM initialization correctly, the bus state controller registers must first be set,

followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address

signal value at that time is latched by a combination of the

CSn, RAS, CAS, and RD/WR signals.

If the value to be set is X, the bus state controller provides for value X to be written to the

SDRAM mode register by performing a write to address H'FFFC5000 + X for area 3 SDRAM. In

this operation the data is ignored, but the mode write is performed as a byte-size access. To set

burst read/single write, CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported

by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 7.18. In

this time 0 is output at the external address pins of A12 or later.

Table 7.18

Access Address in SDRAM Mode Register Write

• Setting for Area 3

Burst read/single write (burst length 1):

Data Bus Width

CAS Latency

Access Address

External Address Pin

16 bits

H'FFFC5440

H'0000440

H'FFFC5460

H'0000460

32 bits

H'FFFC5880

H'0000880

H'FFFC58C0

H'00008C0

Burst read/burst write (burst length 1):

Data Bus Width

CAS Latency

Access Address

External Address Pin

16 bits

H'FFFC5040

H'0000040

H'FFFC5060

H'0000060

32 bits

H'FFFC5080

H'0000080

H'FFFC50C0

H'00000C0

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