SH7672 datasheet(294/1292 Pages) RENESAS

294 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 268 of 1262

REJ09B0437-0100

Mode register setting timing is shown in figure 7.28. A PALL command (all bank pre-charge

command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An

MRS command (mode register write command) is finally issued. Idle cycles, of which number is

specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the

first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,

are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which

number is one or more, are inserted between the MRS and a command to be issued next.

It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after

power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse

width of the reset signal is longer than the idle time, mode register setting can be started

immediately after the reset, but care should be taken when the pulse width of the reset signal is

shorter than the idle time.

Tpw

Trr

Trc

Tmw

Hi-Z

Tnop

Trc

Trr

Trc

REF

MRS

PALL

CKIO

A25 to A0

CSn

RD/

RASL, RASU

DQMxx

D31 to D0

DACKn*2

A12/A11*1

CASL, CASU

Notes: 1. Address pin to be connected to pin A10 of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 7.28

SDRAM Mode Write Timing (Based on JEDEC)

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