SH7672 datasheet(308/1292 Pages) RENESAS

308 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 282 of 1262

REJ09B0437-0100

(2)

Basic Timing for I/O Card Interface

Figures 7.40 and 7.41 show the basic timing for the PCMCIA I/O card interface.

When accessing an I/O card through the PCMCIA interface, be sure to access the space as cache-

disabled.

Switching between I/O card and IC memory card interfaces in the respective address spaces is

accomplished by the SA[1:0] bit settings in CS5WCR and CS6WCR.

The

IOIS16 pin can be used for dynamic adjustment of the width of the I/O bus in access to an I/O

card via the PCMCIA interface when little endian mode has been selected. When the bus width of

area 5 or 6 is set to 16 bits and the

IOIS16 signal is driven high during a cycle of word-unit access

to the I/O card bus, the bus width will be recognized as 8 bits and only 8 bits of data will be

accessed during the current cycle of the I/O card bus. Operation will automatically continue with

access to the remaining 8 bits of data.

The

IOIS16 signal is sampled on falling edges of the CKIO in Tpci0 as well as all Tpci0w cycles

for which the TED3 to TED0 bits are set to 1.5 cycles or more, and the

CE2A and CE2B signals

are updated after 1.5 cycles of the CKIO signal from the sampling point of Tpci0. Ensure that the

IOIS16 signal is defined at all sampling points and does not change along the way.

Set the TED3 to TED0 bits to satisfy the requirement of the PC card in use with regard to setup

timing from

ICIORD or ICIOWR to CE1 or CE2.

The basic waveforms for dynamic bus-size adjustment are shown in figure 7.41.

Since the

IOIS16 signal is not supported in big endian mode, the IOIS16 signal should be fixed to

the low level when big endian mode has been selected.

SH7672 Datasheet(PDF) 308 Page - Renesas Technology Corp