ADS1282IPWR datasheet(12/52 Pages) TI

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OVERVIEW

4th-Order

Modulator

Programmable

DigitalFilter

Serial

Interface

Calibration

Control

AINP1

AVSS

CLK

DVDD

DGND

DIN

DOUT

MCLK

DRDY

SCLK

AINN1

ADS1282

AINN2

AINP2

Over-Range

Detection

BYPAS

LDO

PGA

400W

AVDD+AVSS

400W

+1.8V

(Digitalcore)

300W

RESET

PWDN

SYNC

AVDD

MFLAG

ADS1282

SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008 ........................................................................................................................................ www.ti.com

The ADS1282 is a high-performance analog-to-digital

Gain and offset registers scale the digital filter output

converter (ADC) intended for energy exploration,

to produce the final code value. The scaling feature

seismic

monitoring,

chomatography,

and

other

can be used for calibration and sensor gain matching.

exacting applications. The converter provides 24- or

The output data word is provided as either a 24-bit

32-bit output data in data rates from 250SPS to

word or a

full

32-bit

word,

allowing

complete

4000SPS. Figure 30 shows the block diagram of the

utilization of the inherently high resolution.

ADS1282.

The SYNC input resets the operation of both the

The

two-channel

input

MUX

allows

five

digital

filter

and

the

modulator,

allowing

configurations: Input 1; Input 2; Input 1 and Input 2

synchronization conversions of multiple ADS1282

shorted

together;

shorted

with

400

Ω test;

and

devices to an external event. The SYNC input

common-mode test. The input MUX is followed by a

supports a continuously-toggled input mode that

continuous time PGA, featuring very low noise of

accepts an external data frame clock locked to the

5nV/

√Hz. The PGA is controlled by register settings,

conversion rate.

allowing gains of 1 to 64.

The RESET input resets the register settings and

The

inherently-stable,

fourth-order,

delta-sigma

also restarts the conversion process. The PWDN

modulator measures the differential input signal

input sets the device into a micro-power state. Note

VIN = (AINP – AINN) PGA against the differential

that register settings are not retained in PWDN mode.

reference VREF = (VREFP – VREFN). A digital output

Use the STANDBY command in its place if it is

(MFLAG) indicates that the modulator is in overload

desired to retain register settings (the quiescent

as a result of an overdrive condition. The modulator

current in the Standby mode is slightly higher).

output is available directly on the MCLK, M0, and M1

Noise-immune

Schmitt-trigger

and

clock-qualified

output pins. The modulator connects to an on-chip

inputs

(RESET

and

SYNC)

provide

increased

digital filter that provides the output code readings.

reliability in high-noise environments. The serial

The digital filter consists of a variable decimation rate,

interface is used to read conversion data, in addition

fifth-order sinc filter followed by a variable phase,

to reading from and writing to the configuration

decimate-by-32,

finite-impulse

response

(FIR)

registers.

low-pass filter with programmable phase, and then by

an adjustable high-pass filter for dc removal of the

output reading. The output of the digital filter can be

taken from the sinc, the FIR low-pass, or the infinite

impulse response (IIR) high-pass sections.

Figure 30. ADS1282 Block Diagram

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ADS1282IPWR Datasheet(PDF) 12 Page - Texas Instruments

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