ADS1282IPWR datasheet(23/52 Pages) TI

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MASTER CLOCK INPUT (CLK)

SYNCHRONIZATION

FrequencyRatio(f

)

HP DATA

-0.10

-0.20

-0.30

-0.40

-0.50

0.0001

0.001

0.01

0.1

0.01

0.1

NormalizedFrequency(f/f )

-7.5

-15.0

-22.5

-30.0

-45.0

100

Phase

Amplitude

-37.5

ADS1282

www.ti.com ........................................................................................................................................ SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008

The HPF causes a small gain error, in which case the

magnitude of the error depends on the ratio of

The ADS1282 requires a clock input for operation.

fHP/fDATA. For many common values of (fHP/fDATA), the

The clock is applied to the CLK pin. The data

gain error is negligible. Figure 50 shows the gain

conversion

rate

scales

directly

with

the

CLK

error of the HPF. The gain error factor is illustrated in

frequency. Power consumption versus CLK frequency

Equation 15 (see the Appendix at the end of this

is relatively constant (see the Typical Characteristics).

document).

As with any high-speed data converter, a high-quality,

low-jitter clock is essential for optimum performance.

Crystal clock oscillators are the recommended clock

source. Make sure to avoid excess ringing on the

clock input; keep the clock trace as short as possible

and use a 50

Ω series resistor close to the source.

(SYNC PIN AND SYNC COMMAND)

The ADS1282 can be synchronized to an external

event, as well as synchronized to other ADS1282

devices if the sync event is applied simultaneously.

The ADS1282 has two sources for synchronization:

the SYNC input pin and the SYNC command. The

ADS1282

also

has

two

synchronizing

modes:

Pulse-sync

and

Continuous-sync.

Pulse-sync

Figure 50. HPF Gain Error

mode, the ADS1282 synchronizes to a single sync

event. In Continuous-sync mode, either a single

Figure 51 shows the first-order amplitude and phase

SYNC event is used to synchronize conversions or a

response of the HPF. Note that in the case of

continuous clock is applied to the pin with a period

applying step inputs or synchronizing, the settling

equal to integer multiples of the data rate. When the

time of the filter should be taken into account.

periods of the sync input and the DRDY output do not

match,

the

ADS1282

re-synchronizes

and

conversions are restarted.

Figure 51. HPF Amplitude and Phase Response

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