ADS1282IPWR datasheet(24/52 Pages) TI

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PULSE-SYNC MODE

SystemClock

)

CLK

SYNCCommand

SYNCPin

DRDY

(Pulse-Sync)

SPWL

NewData

Ready

CSHD

SPWH

DRDY

(Continuous-Sync)

DOUT

NewData

Ready

SCSU

CONTINUOUS-SYNC MODE

SystemClock

)

CLK

SYNC

DRDY

CSHD

SCSU

SYNC

1/f

DATA

SPWH

SPWL

ADS1282

SBAS418E – SEPTEMBER 2007 – REVISED OCTOBER 2008 ........................................................................................................................................ www.ti.com

In Pulse-sync mode, the ADS1282 stops and restarts

the conversion process when a sync event occurs (by

pin or command). When the sync event occurs, the

device resets the internal memory; DRDY goes high

(pulse SYNC mode) otherwise in Continuous SYNC

mode, DRDY continues to toggle, and after the digital

filter has settled, new conversion data are available,

as shown in Figure 52 and Table 9.

Note that resynchronization occurs on the next rising

CLK edge after the rising edge of the SYNC pin or

after the eighth rising SCLK edge for opcode SYNC

commands. To be effective, the SYNC opcode should

be broadcast to all devices simultaneously.

Figure 52. Pulse-Sync Timing, Continuous-Sync

Timing with Single Sync

In Continuous-sync mode, either a single sync pulse

or a continuous clock may be applied. When a single

sync pulse is applied (rising edge), the device

behaves similar to the Pulse-sync mode. However, in

this mode, DRDY continues to toggle unaffected but

the DOUT output is held low until data are ready, 63

DRDY periods later. When the conversion data are

non-zero, new conversion data are ready (as shown

in Figure 52).

When a continuous clock is applied to the SYNC pin,

the period must be an integral multiple of the output

data rate or the device re-synchronizes. When the

sync input is first applied, the device re-synchronizes

(under

the

condition

tSYNC ≠ N/fDATA). DRDY

Figure 53. Continuous-Sync Timing with Sync

continues to output but DOUT is held low until the

Clock

new data are ready. Then, if SYNC is applied again

and the period matches an integral multiple of the

output data rate, the device freely runs without

re-synchronization. Note that the phase of the applied

clock and output data rate (DRDY) are not matched

because of the initial delay of DRDY after SYNC is

first

applied.

Figure

shows

the

timing

for

Continuous-Sync mode.

Note that a SYNC clock input should be applied after

the Continuous-Sync mode is set. The first rising

edge of SYNC then causes a synchronization.

Table 9. Pulse-Sync Timing for Figure 52 and Figure 53

PARAMETER

DESCRIPTION

MIN

MAX

UNITS

tSYNC

SYNC period(1)

Infinite

n/fDATA

tCSHD

CLK to SYNC hold time to not latch on CLK edge

tSCSU

SYNC to CLK setup time to latch on CLK edge

tSPWH, L

SYNC pulse width, high or low

1/fCLK

Time for data ready (SINC filter)

See Appendix, Table 23

tDR

Time for data ready (FIR filter)

62.98046875/fDATA + 466/fCLK

(1)

Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization.

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