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38K2 Datasheet(PDF) 349 Page - Renesas Technology Corp

Part # 38K2
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  358 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

38K2 Datasheet(HTML) 349 Page - Renesas Technology Corp

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Addressing mode
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
7
6
5
4
3
2
1
0
Processor status register
NV
T
B
D
I
Z
C
OP n
# OP n
# OP n
# OP n
# OP n
# OP n
# OP n
#
OP n
#
OP n
#
OP n
# OP n
#
3.6 Machine instructions
Rev.2.00
Oct 15, 2006
page 91 of 99
38K2 Group
REJ09B0338-0200
APPENDIX
Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n# OP n# OP n# OP n# OP n#
OP n
#
3.6 Machine instructions
Rev.2.00
Oct 15, 2006
page 90 of 99
38K2 Group
REJ09B0338-0200
APPENDIX
E2 16 2
4D
EE
4
6
3
3
5D
FE
5
7
3
3
59 5
3
N
N
•
N
N
N
N
•
•
N
•
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
Z
Z
Z
Z
•
•
Z
•
Z
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
41 6
2 51 6
2
B5
B4
4C
20
AD
AE
AC
6C
A1
4
4
2
2
B6 4
2
3
6
4
4
4
3
3
3
3
3
BD
BC
5
5
B9
BE
5
5
3
3
3
3
53 B2
02
4
7
2
2
62 B1 62
22 5
2
55
F6
4
6
2
2
This instruction subtracts one from the current
contents of X.
This instruction subtracts one from the current
contents of Y.
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction adds one to the contents of A
or M.
This instruction adds one to the contents of X.
This instruction adds one to the contents of Y.
This instruction jumps to the address desig-
nated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
This instruction stores the contents of the PC
in the stack, then jumps to the address desig-
nated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
When T = 0, this instruction transfers the con-
tents of M to A.
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction loads the immediate value in
M.
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
DEX
DEY
DIV
EOR
(Note 1)
INC
INX
INY
JMP
JSR
LDA
(Note 2)
LDM
LDX
LDY
X
← X – 1
Y
← Y – 1
A
← (M(zz + X + 1),
M(zz + X )) / A
M(S)
← one's comple-
ment of Remainder
S
← S – 1
When T = 0
A
← A V– M
When T = 1
M(X)
← M(X) V– M
A
← A + 1 or
M
← M + 1
X
← X + 1
Y
← Y + 1
If addressing mode is ABS
PCL
← ADL
PCH
← ADH
If addressing mode is IND
PCL
← M (ADH, ADL)
PCH
← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL
← M(00, ADL)
PCH
← M(00, ADL + 1)
M(S)
← PCH
S
← S – 1
M(S)
← PCL
S
← S – 1
After executing the above,
if addressing mode is ABS,
PCL
← ADL
PCH
← ADH
if addressing mode is SP,
PCL
← ADL
PCH
← FF
If addressing mode is ZP, IND,
PCL
← M(00, ADL)
PCH
← M(00, ADL + 1)
When T = 0
A
← M
When T = 1
M(X)
← M
M
← nn
X
← M
Y
← M
3A 21
1
1
1
1
2
2
2
2
CA
88
E8
C8
45
E6
3
5
2
2
49 22
A9
A2
A0
A5
3C
A6
A4
3
4
3
3
2
3
2
2
2
2
2
2
2
2



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