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38K2 Datasheet(PDF) 351 Page - Renesas Technology Corp

Part # 38K2
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  358 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

38K2 Datasheet(HTML) 351 Page - Renesas Technology Corp

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Addressing mode
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
ZP, IND
IND, X
IND, Y
REL
SP
7
6
5
4
3
2
1
0
Processor status register
NV
T
B
D
I
Z
C
OP n
# OP n
# OP n
# OP n
# OP n
# OP n
# OP n
#
OP n
#
OP n
#
OP n
# OP n
#
3.6 Machine instructions
Rev.2.00
Oct 15, 2006
page 95 of 99
38K2 Group
REJ09B0338-0200
APPENDIX
Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n# OP n# OP n# OP n# OP n#
OP n
#
3.6 Machine instructions
Rev.2.00
Oct 15, 2006
page 94 of 99
38K2 Group
REJ09B0338-0200
APPENDIX
•
•
•
•
N
N
N
N
N
•
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
Z
Z
Z
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
3
35
FD
4
ED
2
4
F5
F9 5
3
E1 6
2 F1 6
2
95
94
5
5
2
2
96 52
8D
8E
8C
5
5
5
3
3
3
9D 6
3 99 6
3
81 7
2 91 7
2
N
•
•
•
•
•
V
•
•
•
•
•
•
•
•
•
•
1
•
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•
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1
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1
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Z
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C
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1
•
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•
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
This instruction sets the designated bit i of A
or M.
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
This instruction stores the contents of X in M.
The contents of X does not change.
This instruction stores the contents of Y in M.
The contents of Y does not change.
This instruction stores the contents of A in X.
The contents of A does not change.
This instruction stores the contents of A in Y.
The contents of A does not change.
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
This instruction transfers the contents of S in
X.
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
SBC
(Note 1)
(Note 5)
SEB
SEC
SED
SEI
SET
STA
STP
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
When T = 0
_
A
← A – M – C
When T = 1
_
M(X)
← M(X) – M – C
Ai or Mi
← 1
C
← 1
D
← 1
I
← 1
T
← 1
M
← A
M
← X
M
← Y
X
← A
Y
← A
M = 0?
X
← S
A
← X
S
← X
A
← Y
85
86
84
64
4
4
4
3
2
2
2
2
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
E9 2
2
0B
+
20i
0F
+
20i
21
52
E5 3
2
38
F8
78
32
2
2
2
2
1
1
1
1
42
AA
A8
BA
8A
9A
98
C2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1



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