38K2 datasheet(101/358 Pages) RENESAS

101 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 82 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

EXB Operation Timing Diagram

(1) CPU Channel Receiving Operation

CPU channel receiving operation is shown bellow.

Fig. 122 CPU channel receiving operation

➀➁

➂

Address ExA0

Chip select ExCS

A0 = “1”

CS = “0”

A0 = “1”

CS = “0”

Read ExRD

➁

Write ExWR

Data DQ0 to DQ7

Internal clock

Interrupt request ExINT

[RxB_RDY]

RxB_RDY

Receive buffer full bit RXB_FULL

Receive buffer RXBUF

Transmit buffer TXBUF

➀

CPU channel receive enable bit

RXB_ENB

Receive buffer read

➂

External I/O configuration register

INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt)

EXB interrupt source enable register

RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)

➀ Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.

If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an

external are inactive.

➁ When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:

• The data is written into the receive buffer (RXBUF)

• Negation of the receive buffer ready signal (RxB_RDY) to an external is made

• The RXB_FULL interrupt is generated.

➂ When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.

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