38K2 datasheet(102/358 Pages) RENESAS

102 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 83 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

(2) CPU Channel Transmitting Operation

CPU channel transmitting operation is shown bellow.

Fig. 123 CPU channel tranmitting operation

TxB_RDY

➀

➁

➁’

➂

Address ExA0

Chip select ExCS

Read ExRD

Write ExWR

Data DQ0 to DQ7

Internal clock

Interrupt request ExINT

[TxB_RDY]

Transmit buffer empty bit

TXB_EMPTY

Receive buffer RXBUF

Transmit buffer TXBUF

CPU channel transmit enable bit

TXB_ENB

Transmit data write

External I/O configuration register

INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt)

EXB interrupt source enable register

TXB_ENB (CPU channel transmit enable) = “1” (Transmit buffer empty interrupt enabled)

➀ Writing the command for enabling operation generates TXB_EMPTY interrupt.

If the CPU channel transmit enable bit (TXB_ENB) is “0”, both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to

an external are inactive.

➁ When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared

to “0” and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made.

➂ When a read operation is performed from an external MCU bus in the condition of ExCS = “L” and ExA0 = “H”, it will result in as follows:

• The contents of the transmit buffer (TXBUF) is read out

• The transmit buffer empty bit (TXB_EMPTY) is set to “1”

• Negation of the transmit buffer ready signal (TxB_RDY) to an external is made.

A0 = “1”

CS = “0”

A0 = “1”

CS = “0”

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