Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

38K2 Datasheet(PDF) 108 Page - Renesas Technology Corp

Part # 38K2
Description  RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  358 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

38K2 Datasheet(HTML) 108 Page - Renesas Technology Corp

Back Button 38K2 Datasheet HTML 104Page - Renesas Technology Corp 38K2 Datasheet HTML 105Page - Renesas Technology Corp 38K2 Datasheet HTML 106Page - Renesas Technology Corp 38K2 Datasheet HTML 107Page - Renesas Technology Corp 38K2 Datasheet HTML 108Page - Renesas Technology Corp 38K2 Datasheet HTML 109Page - Renesas Technology Corp 38K2 Datasheet HTML 110Page - Renesas Technology Corp 38K2 Datasheet HTML 111Page - Renesas Technology Corp 38K2 Datasheet HTML 112Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 108 / 358 page
background image
FUNCTIONAL DESCRIPTION
Rev.2.00
Oct 15, 2006
page 89 of 130
38K2 Group
REJ09B0338-0200
HARDWARE
MULTICHANNEL RAM
The 38K2 group has the built-in multichannel RAM including the
small logic circuit (RAM I/F) instead of ordinary RAM.
The multichannel RAM has the USB channel and the EXB channel
in addition to the CPU channel.
The multichannel RAM controls access from CPU, USB and EXB,
synchronizing control with
φ. The USB transfer rate is about 1.5
Mbytes/second. Access to the multichannel RAM is performed at
every about 5.3 clocks in
φ = 8 MHz, or at every about 4 clocks in
φ = 6 MHz. The USB’s access has priority to the EXB’s.
The one wait function (ONW function) of 38000 series CPU is
used internally to control access with the CPU. When receiving an
access request from the USB or the EXB, the multichannel RAM
outputs ONW signal to wait the CPU for one clock, and access of
the USB or the EXB is performed.
If the multichannel RAM is outputting ONW signal while the CPU
is in the state of reading/writing for the RAM area, the CPU read
cycle or write cycle is extended by 1 period of
φ.
Fig. 129 Multichannel RAM timing diagram (no wait)
φ
CPU AD
RD/WR
USB REQ
EXB REQ
ONW
RAM access right
RAM RD/WR
CPU bus cycle
Multichannel RAM
RAM bus cycle
CPU
USB
CPU
RAM area
Except RAM
RAM area
No wait
No wait
No wait
Except RAM
No RD/WR
φ
CPU AD
RD/WR
USB REQ
EXB REQ
ONW
RAM access right
RAM RD/WR
One wait
2-cycle wait (max.) for EXB
Prior CPU
Prior CPU
Prior USB
RAM area
One wait
USB having priority of USB/EXB
simultaneous access
Prior CPU
RAM area
CPU
CPU
CPU
EXB
CPU
USB
USB
RAM area
EXB
Multichannel RAM
RAM bus cycle
CPU bus cycle
One wait
Prohibiting continuous access of
USB/EXB
CPU accessing RAM at the latter part
One wait
RAM area
Fig. 130 Multichannel RAM timing diagram (one wait)
ONW = “H”



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com