38K2 datasheet(131/358 Pages) RENESAS

131 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 112 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

(3) Standard Serial I/O Mode

The standard serial I/O mode inputs and outputs the software

commands, addresses and data needed to operate (read, pro-

gram, erase, etc.) the internal flash memory. This I/O is clock

synchronized serial. This mode requires a purpose-specific pe-

ripheral unit.The standard serial I/O mode is different from the

parallel I/O mode in that the CPU controls flash memory rewrite

(uses the CPU rewrite mode), rewrite data input and so forth. The

standard serial I/O mode is started by connecting “H” to the P16

(CE) pin and “H” to the P42 (SCLK) pin and “H” to the CNVSS (VPP)

pin (apply 4.5 V to 5.25 V to Vpp from an external source), and re-

leasing the reset operation. (In the ordinary microcomputer mode,

set CNVss pin to “L” level.)

This control program is written in the Boot ROM area when the

product is shipped from Renesas Technology Corp.. Accordingly,

make note of the fact that the standard serial I/O mode cannot be

used if the Boot ROM area is rewritten in parallel I/O mode. Figure

154 shows the pin connections for the standard serial I/O mode.

In standard serial I/O mode, serial data I/O uses the four serial I/O

pins SCLK, RxD, TxD and SRDY (BUSY). The SCLK pin is the trans-

fer clock input pin through which an external transfer clock is

input. The TxD pin is for CMOS output. The SRDY (BUSY) pin out-

puts “L” level when ready for reception and “H” level when

reception starts.

Serial data I/O is transferred serially in 8-bit units.

In standard serial I/O mode, only the User ROM area shown in

Figure 146 can be rewritten. The Boot ROM area cannot.

In standard serial I/O mode, a 7-byte ID code is used. When there

is data in the flash memory, commands sent from the peripheral

unit (programmer) are not accepted unless the ID code matches.

Outline Performance (Standard Serial I/O Mode)

In standard serial I/O mode, software commands, addresses and

data are input and output between the MCU and peripheral units

(serial programer, etc.) using 4-wire clock-synchronized serial I/O.

In reception, software commands, addresses and program data

are synchronized with the rise of the transfer clock that is input to

the SCLK pin, and are then input to the MCU via the RxD pin. In

transmission, the read data and status are synchronized with the

fall of the transfer clock, and output from the TxD pin.

The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB

first.

When busy, such as during transmission, reception, erasing or

program execution, the SRDY (BUSY) pin is “H” level. Accordingly,

always start the next transfer after the SRDY (BUSY) pin is “L”

level.

Also, data and status registers in a memory can be read after in-

putting software commands. Status, such as the operating state of

the flash memory or whether a program or erase operation ended

successfully or not, can be checked by reading the status register.

Here following explains software commands, status registers, etc.

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