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38K2 Datasheet(PDF) 199 Page - Renesas Technology Corp |
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38K2 Datasheet(HTML) 199 Page - Renesas Technology Corp |
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199 / 358 page ![]() 2.4 Serial I/O Rev.2.00 Oct 15, 2006 page 50 of 112 38K2 Group REJ09B0338-0200 APPLICATION Fig. 2.4.16 Registers setting related to receiving side b7 b0 Receiving side Serial I/O control register (Address : 0FE016) SIOCON Serial I/O synchronous clock selection bit : External clock SRDY output enable bit : SRDY output enabled Transmit enable bit : Transmit enabled Set this bit to “1”, using SRDY output. Receive enable bit : Receive enabled Serial I/O mode selection bit : Clock synchronous serial I/O Serial I/O enable bit : Serial I/O enabled 1 1 1 1 1 1 Serial I/O status register (Address : 2716) SIOSTS b7 b0 Receive buffer full flag Confirm completion of receiving 1-byte data with this flag. “1” : At completing reception “0” : At reading out contents of Receive buffer register Overrun error flag “1” : When data is ready in Receive shift register while Receive buffer register contains the data. Parity error flag “1” : When a parity error occurs in enabled parity. Framing error flag “1” : When stop bits cannot be detected at the specified timing. Summing error flag “1” : when any one of the following errors occurs. • Overrun error • Parity error • Framing error |
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