38K2 datasheet(206/358 Pages) RENESAS

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2.4 Serial I/O

Rev.2.00

Oct 15, 2006

page 57 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

The communication is performed according to the timing shown in Figure 2.4.25. In the slave unit,

when a synchronous clock is not input within a certain time (heading adjustment time), the next clock

input is processed as the beginning (heading) of a block.

When a clock is input again after one block (8 byte) is received, the clock is ignored.

Figure 2.4.26 shows related registers setting.

Fig. 2.4.25 Timing chart

Fig. 2.4.26 Related registers setting

Byte cycle

Block transfer term

Block transfer cycle

Interval between blocks

Processing for heading adjustment

Heading adjustment time

Master unit

Transmit enabled

SIOCON

Serial I/O control register (Address : 0FE016)

Synchronous clock : BRG/4

Transmit interrupt source :

Transmit shift operating completion

Receive enabled

Clock synchronous serial I/O

Serial I/O enabled

BRG count source : f(XIN)

SRDY

output disabled

Not affected by external clock

Transmit enabled

SIOCON

Serial I/O control register (Address : 0FE016)

Not use the serial I/O transmit interrupt

Receive enabled

Clock synchronous serial I/O

Slave unit

Serial I/O enabled

Synchronous clock : External clock

Both of units

BRG

Baud rate generator (Address : 0FE216)

Set “division ratio – 1”.

SRDY

output disabled

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