38K2 datasheet(230/358 Pages) RENESAS

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2.9 Watchdog timer

Rev.2.00

Oct 15, 2006

page 81 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

Fig. 2.9.6 Control procedure

Fig. 2.9.5 Related registers setting

2.9.4 Notes on watchdog timer

qMake sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog

timer keeps counting during that term.

qWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.

CPUM

WDTCON

CPU mode register (address 3B16)

Processor mode: Single-chip mode

System clock: Main clock

System clock division ratio: f(system clock) (Through mode)

Watchdog timer H (for read-out of high-order 6 bits)

Watchdog timer control register (address 3916)

Enable STP instruction

Watchdog timer H count source: Watchdog timer L underflow

0 1

Initialization

SEI

CLT

CLD

CPUM (address 3B16)

← 11001X002

CLI

WDTCON (address 3916), bit7,bit6

002

RESET

Main processing

•Processor mode: Single-chip mode

•Main clock f(XIN): Operating

•Through mode selected as main clock division ratio

•Watchdog timer L underflow selected as Watchdog

timer H count source

•STP instruction enabled

•Interrupts enabled

•All interrupts disabled

38K2 Datasheet(PDF) 230 Page - Renesas Technology Corp

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