38K2 datasheet(234/358 Pages) RENESAS

234 / 358 page

2.11 Frequency synthesizer (PLL)

Rev.2.00

Oct 15, 2006

page 85 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

Fig. 2.11.3 Structure of CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

R W

b1 b0

0 0 : Single-chip mode

0 1 : Not available

1 0 : Not available

1 1 : Not available

Name

Function

At reset

0 : 0 page

1 : 1 page

CPU mode register

(CPUM: address 3B16)

CPU mode register

Processor mode bits

Stack page selection bit

Fix this bit to “1”.

Fix this bit to “0”.

0 : Main clock f(XIN)

1 : fSYN

System clock selection bit

b7 b6

0 0 :

φ = f(system clock)/8 (8-divide mode)

0 1 :

φ = f(system clock)/4 (4-divide mode)

1 0 :

φ = f(system clock)/2 (2-divide mode)

1 1 :

φ = f(system clock) (Through mode)

System clock division ratio

selection bits

*: The initial value of bit 1 depends on the CNVss level.

Fig. 2.11.4 Structure of PLL control register

b7 b6 b5 b4 b3 b2 b1 b0

USB clock division

ratio selection bits

PLL control register (PLLCON)

[Address : 0FF816]

Function

At reset

Name

PLL control register

b4 b3

0 0 : Divided by 8 (fSYN = fUSB/8)

0 1 : Divided by 6 (fSYN = fUSB/6)

1 0 : Divided by 4 (fSYN = fUSB/4)

1 1 : Not selected

Nothing is arranged for these bit. These are write disabled bits.

When these bits are read out, the contents are “0”.

b6 b5

0 0 : Not multiplied (fVCO = fXIN)

0 1 : Double (fVCO = fXIN ✕ 2)

1 0 : Quadruple (fVCO = fXIN ✕ 4)

1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)

PLL operation mode

selection bits

PLL enable bit

0 : Disabled

1 : Enabled

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