38K2 datasheet(238/358 Pages) RENESAS

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2.11 Frequency synthesizer (PLL)

Rev.2.00

Oct 15, 2006

page 89 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

q X: This bit is not used here.

Set it to “0” or “1” arbitrarily.

•Select main clock f(XIN) as a USB clock

•PLL operation mode (bit6,5): Multiplied by 8

•USB division mode (bit4,3): Divided by 6

•Enable PLL operation (bit7)

•Select fSYN (8MHZ) as a system clock

•Select PLL circuit output clock fVCO as a USB clock

•Wait for oscillation stabilization

When multiplying oscillation by PLL, wait for oscillation

stabilization.

CPUM (address: 3B16)

← 11101X002

USBCON (address: 1016)

← X0XXXXXX2

PLLCON (address: 0FF816)

← 111010002

Wait (approximately 1 ms)

USBCON (address: 1016)

← X1XXXXXX2

Same setting procedure when hardware reset

PLLCON (address: 0FF816) bit6,5

← 002

•PLL operation mode (bit6,5): Not multiplied

(Change PLL circuit output clock fVCO to f(XIN))

After recovery from stop mode

Note: The above setting example assumes the operation when the external oscillating clock is 6 MHZ and

the internal system clock is fSYN.

Fig. 2.11.8 Related registers setting when recovery from stop mode

2.11.4 Notes on PLL

q6 MHZ or 12 MHZ external oscillator can be connected as an input reference clock (f(XIN)). When using

the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN)

as an input clock reference for the PLL.

qWhen enabling PLL operation from PLL disabled status (disabled when reset), set the USB clock select

bit of USBCON to “0” (f(XIN)) to operate with the main clock (f(XIN)).

qWhen supplying fVCO to the USB block after setting PLL operation enable bit to “1” (PLL enabled), wait

for the oscillation stable time (1 ms or less) of PLL to avoid any instability caused by the clock, then set

USB clock select bit to “1” (USB clock).

qWhen selecting fSYN as an internal system clock, fUSB must be 48 MHz.

qWhen selecting fSYN as an internal system clock, change the system clock selection bit to main clock

(f(XIN)) before executing STP instruction. It is because the following are needed for the low-power consumption:

•fUSB must be stopped by disabling PLL operation in Stop mode.

•The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input

count source.

38K2 Datasheet(PDF) 238 Page - Renesas Technology Corp

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