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38K2 Datasheet(PDF) 242 Page - Renesas Technology Corp |
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38K2 Datasheet(HTML) 242 Page - Renesas Technology Corp |
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242 / 358 page  2.12 Clock generating circuit Rev.2.00 Oct 15, 2006 page 93 of 112 38K2 Group REJ09B0338-0200 APPLICATION (2) Generation of internal clock f( φφφφφ) using fSYN (fUSB division clock) Table 2.12.2 shows the example of internal clock f( φ) generation using fSYN; Figure 2.12.6 shows the related registers setting. Table 2.12.2 Example of internal clock f( φφφφφ) generation using fSYN fSYN 6 MHZ 8 MHZ 12 MHZ System clock division ratio selection bits *2 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 0.75 MHZ 1.5 MHZ 3 MHZ 6 MHZ 1 MHZ 2 MHZ 4 MHZ 8 MHZ 1.5 MHZ 3 MHZ 6 MHZ Power source voltage VCC [V] 3.00 to 5.25 4.00 to 5.25 f( φ) *1: PLL control register (bits 4,3) *2: CPU mode register (bits 7,6) fUSB 48 MHZ USB clock division ratio selection bits *1 0 0 0 1 1 1 |
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