38K2 datasheet(241/358 Pages) RENESAS

241 / 358 page

2.12 Clock generating circuit

Rev.2.00

Oct 15, 2006

page 92 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

2.12.3 Oscillation control

Either can be selected as an internal system clock between the following two by system clock selection

bit.

q Main clock f(XIN)

q fSYN (fUSB division clock)

Any one can be selected as an internal clock

φ among the following four by system clock division ratio

selection bits.

q f(XIN) or fSYN/8 (8-divide mode)

q f(XIN) or fSYN/4 (4-divide mode)

q f(XIN) or fSYN/2 (2-divide mode)

q f(XIN) or fSYN (Through mode)

(1)

Generation of internal clock f(

φφφφφ) using main clock f(XIN)

Table 2.12.1 shows the example of internal clock f(

φ) generation using main clock f(XIN); Figure

2.12.5 shows the related registers setting.

Table 2.12.1 Example of internal clock f(

φφφφφ) generation using main clock f(XIN)

System clock

6 MHZ

8 MHZ

12 MHZ

System clock division

ratio selection bits *

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

0 0

0 1

1 0

0.75 MHZ

1.5 MHZ

3 MHZ

6 MHZ

1 MHZ

2 MHZ

4 MHZ

8 MHZ

1.5 MHZ

3 MHZ

6 MHZ

Power source voltage

VCC [V]

3.00 to 5.25

4.00 to 5.25

φ)

*: CPU mode register (bits 7,6)

Fig. 2.12.5 Related registers setting

CPU mode register

(CPUM: address 3B16)

0 : Main clock f(XIN)

b7 b6

0 0 :

φ = f(system clock)/8 (8-divide mode)

0 1 :

φ = f(system clock)/4 (4-divide mode)

1 0 :

φ = f(system clock)/2 (2-divide mode)

1 1 :

φ = f(system clock) (Through mode)

q Select main clock f(XIN) as system clock and set clock division mode

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