38K2 datasheet(236/358 Pages) RENESAS

236 / 358 page

2.11 Frequency synthesizer (PLL)

Rev.2.00

Oct 15, 2006

page 87 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

Table 2.11.2 USB clock division ratio selection bits setting example

fUSB

6 MHZ

8 MHZ

12 MHZ

USB clock division

ratio selection bits *

48 MHZ

fSYN

q fSYN (fUSB division clock)

According to the setting of the USB clock division ratio selection bits (bits 4, 3 of PLLCON), the

division clock of fUSB is supplied to fSYN.

fSYN =fUSB / m, m:value selected by USB clock division ratio selection bits

Set the USB clock division ratio selection bits so that fSYN may be set to 6 MHz, 8 MHz or 12 MHz.

When using fSYN as internal system clock, set the system clock selection bit of CPU mode register

(bit 5 of CPUM: address 003B16) to “1” (fSYN).

Table 2.11.2 shows the example of USB clock division ratio selection bits setting.

*: PLL control register (bit4,3)

q Setting for starting up PLL circuit when hardware reset

Figure 2.11.6 shows the example of related registers setting.

Fig. 2.11.6 Related registers setting when hardware reset

q X: This bit is not used here.

Set it to “0” or “1” arbitrarily.

•Select main clock f(XIN) as a system clock

•Select main clock f(XIN) as a USB clock

•PLL operation mode (bit6,5): Multiplied by 8

•USB division mode (bit4,3): Divided by 6

•Enable PLL operation (bit7)

•Select fSYN as a system clock

•Select PLL circuit output clock fVCO as a USB clock

Note: The above setting example assumes the operation when the external oscillating clock is 6 MHZ and

the internal system clock is fSYN.

•Wait for oscillation stabilization

When multiplying oscillation by PLL, wait for oscillation

stabilization.

CPUM (address: 3B16)

← 11001X002

CPUM (address: 3B16)

← 11101X002

USBCON (address: 1016)

← X0XXXXXX2

PLLCON (address: 0FF816)

← 111010002

Wait (approximately 1 ms)

USBCON (address: 1016)

← X1XXXXXX2

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