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SH7014 Datasheet(PDF) 465 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 465 Page - Renesas Technology Corp |
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465 / 754 page ![]() 15. Compare Match Timer (CMT) Rev.5.00 Sep. 27, 2007 Page 431 of 716 REJ09B0398-0500 15.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T 2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write. Figure 15.8 shows the timing when an increment occurs during the T 2 state of the CMCNTH write cycle. T1 T2 CK Address Internal write signal CMCNT input clock CMCNTH CMCNT write cycle CMCNTH N M CMCNTH write data X X CMCNTL Figure 15.8 CMCNT Byte Write and Increment Contention |
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