SH7014 datasheet(461/754 Pages) RENESAS

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15. Compare Match Timer (CMT)

Rev.5.00 Sep. 27, 2007 Page 427 of 716

REJ09B0398-0500

15.4

Interrupts

15.4.1

Interrupt Sources

The CMT has a compare match interrupt for each channel, with independent vector addresses

allocated to each of them. The corresponding interrupt request is output when the interrupt request

flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1.

When activating CPU interrupts by interrupt request, the priority between the channels can be

changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details.

15.4.2

Compare Match Flag Set Timing

The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the

CMCOR register and the CMCNT counter match. The compare match signal is generated upon

the final state of the match (timing at which the CMCNT counter matching count value is

updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare

match signal will not be generated until a CMCNT counter input clock occurs. Figure 15.4 shows

the CMF bit set timing.

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