SH7014 datasheet(457/754 Pages) RENESAS

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15. Compare Match Timer (CMT)

Rev.5.00 Sep. 27, 2007 Page 423 of 716

REJ09B0398-0500

15.2.2

Compare Match Timer Control/Status Register (CMCSR)

The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the

occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock

used for incrementation. It is initialized to H'0000 by power-on resets and by standby mode.

Bit:

⎯

Initial value:

R/W:

Bit:

CMF

CMIE

⎯

CKS1

CKS0

Initial value:

R/W:

R/(W)*

R/W

Note:

The only value that can be written is a 0 to clear the flag.

Bits 15 to 8 and 5 to 2

⎯Reserved: These bits always read as 0. The write value should always be

Bit 7

⎯Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and

CMCOR values have matched.

Bit 7

CMF

Description

CMCNT and CMCOR values have not matched

(initial status)

Clear condition: Write a 0 to CMF after reading a 1 from it

CMCNT and CMCOR values have matched

Bit 6

⎯Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a

compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1).

Bit 6

CMIE

Description

Compare match interrupts (CMI) disabled

(initial status)

Compare match interrupts (CMI) enabled

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