SH7014 datasheet(480/754 Pages) RENESAS

480 / 754 page

16. Pin Function Controller (PFC)

Rev.5.00 Sep. 27, 2007 Page 446 of 716

REJ09B0398-0500

16.3.2

Port A Control Registers L1, L2 (PACRL1 and PACRL2)

PACRL1 and PACRL2 are 16-bit read/write registers that select the functions of the 16

multiplexed pins of port A (11 pins in the SH7014). PACRL1 selects the function of the PA15/CK

to PA8/TCLKC/

IRQ2 pins of port A; PACRL2 selects the function of the PA7/TCLKB/CS3 to

PA0/RXD0 pins of port A.

Port A includes bus control signals (

RD, WRH, WRL, CS0 to CS3, and AH) and DMAC control

signals (

DREQ0 and DREQ1), but in the SH7016 and SH7017, register settings relating to the

selection of these pin functions may be invalid depending on the operating mode. For details, see

table 16.2, Pin Functions in Each Operating Mode.

PACRL1 is initialized by external power-on reset to H'4000 in extended mode, and to H'0000 in

single chip mode. PACRL2 is initialized by external power-on reset to H'0000. Neither register is

initialized by reset by WDT, standby mode, or sleep mode, so the previous data is maintained.

The settings of bits 12, 10, 8, 6, and 4 of PACRL1 are functional only in the SH7016 and SH7017.

In the SH7014, there are no pins corresponding to these bits; they are always read as 0, and their

write value should always be 0.

Port A Control Register L1 (PACRL1):

Bit:

⎯

PA15MD

⎯

PA14MD

⎯

PA13MD

⎯

PA12MD

Initial value:

0 (1)

R/W:

R/W

Bit:

⎯

PA11MD

⎯

PA10MD PA9MD1 PA9MD0 PA8MD1 PA8MD0

Initial value:

R/W:

R/W*

R/W

Notes: 1. Bit 14 is initialized to 1 in extended mode.

2. R only in the SH7014.

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