SH7014 datasheet(531/754 Pages) RENESAS

531 / 754 page

18. 128 kB Flash Memory (F-ZTAT)

Rev.5.00 Sep. 27, 2007 Page 497 of 716

REJ09B0398-0500

18.4

The registers used to control the on-chip flash memory when enabled are shown in table 18.3.

Table 18.3

Flash Memory Registers

Abbreviation

R/W

Initial Value

Address

Access Size

Flash memory control

FLMCR1

R/W*

H'00*

H'FFFF8580

Flash memory control

FLMCR2

H'00

H'FFFF8581

Erase block register 1

EBR1

R/W*

H'00*

H'FFFF8582

RAM emulation register

RAMER

R/W

H'0000

H'FFFF8628

8, 16, 32

Notes: FLMCR1, FLMCR2, and EBR1 are 8-bit registers, and RAMER is a 16-bit register.

Only byte accesses are valid for FLMCR1, FLMCR2, and EBR1, the access requiring 3

cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a

longword access.

When a longword write is performed on RAMER, 0 must always be written to the lower

word (address H'FFFF8630). Operation is not guaranteed if any other value is written.

1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and

writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1.

2. A read in a mode in which on-chip flash memory is disabled will return H'00.

3. When a low level is input to the FWP pin, the initial value is H'80.

4. When a high level is input to the FWP pin, or if a low level is input and the SWE bit in

FLMCR1 is not set, these registers are initialized to H'00.

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