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SH7014 Datasheet(PDF) 143 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 143 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 109 of 716
REJ09B0398-0500
8.2.2
Bus Control Register 2 (BCR2)
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and
CS signal assert
extension of each CS space.
BCR2 is initialized by power-on resets to H'FFFF, but is not initialized by software standbys.
Bit:
15
14
13
12
11
10
9
8
IW31
IW30
IW21
IW20
IW11
IW10
IW01
IW00
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
CW3
CW2
CW1
CW0
SW3
SW2
SW1
SW0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 8
⎯Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00):
These bits specify idle cycles inserted between consecutive accesses when the second one is to a
different CS area after a read. Idles are used to prevent data conflict between ROM (and other
memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even
when access is to the same area, idle cycles must be inserted when a read access is followed
immediately by a write access. The idle cycles to be inserted comply with the area specification of
the previous access
. Refer to section 8.6, Waits between Access Cycles, for details.
IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between
cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00
specify the idle between cycles for CS0 space.
Bit 15
IW31
Bit 14
IW30
Description
0
0
No idle cycle after accessing CS3 space
1
Inserts one idle cycle
1
0
Inserts two idle cycles
1
Inserts three idle cycles
(initial value)



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