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SH7014 Datasheet(PDF) 175 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 175 Page - Renesas Technology Corp |
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175 / 754 page  8. Bus State Controller (BSC) Rev.5.00 Sep. 27, 2007 Page 141 of 716 REJ09B0398-0500 CK CSn CSm RD Data CSn space read CSm space write Idle cycle WRx Address T1 T2 T1 T2 Tidle Figure 8.20 Idle Cycle Insertion Example IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. DIW specifies the number of idle cycles required, after a DRAM space read either to read other external spaces (CS space), or for this LSI, to do write accesses. 0 to 3 cycles can be specified for CS space, and 0 to 1 cycle for DRAM space. |
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