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SH7014 Datasheet(PDF) 176 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 176 Page - Renesas Technology Corp |
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176 / 754 page  8. Bus State Controller (BSC) Rev.5.00 Sep. 27, 2007 Page 142 of 716 REJ09B0398-0500 8.6.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of the BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 8.21 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write accessed. CK CSn RD WRx Data CSn space access CSn space access Idle cycle Address T1 T2 T1 T2 Tidle Figure 8.21 Same Space Consecutive Access Idle Cycle Insertion Example |
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