SH7014 datasheet(179/754 Pages) RENESAS

179 / 754 page

8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 145 of 716

REJ09B0398-0500

SH7014/16/17

RAS

RDWR

A0 to A9

CASL

AD0 to AD7

RAS

A0 to A9

CAS

I/O0 to I/O7

512 k

× 8 bits

DRAM

Figure 8.26 8-Bit Data Bus Width DRAM Connection

RAS

RDWR

A1 to A9

CASH

UCAS

CASL

LCAS

AD0 to AD15

I/O0 to I/O15

SH7014/16/17

256 k

× 16 bits

DRAM

A0 to A8

Figure 8.27 16-Bit Data Bus Width DRAM Connection

8.9

On-chip Peripheral I/O Register Access

On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 8.5.

Table 8.5

On-chip Peripheral I/O Register Access

On-chip Peripheral

Module

SCI

MTU

INTC

PFC,

PORT

CMT

A/D*

WDT

DMAC

CACHE

Connected bus width

8bit

16bit

Access cycle

2cyc

3cyc

Note:

The A/D in the SH7016 and SH7017 has an 8-bit width and is accessed in 3 cyc.

SH7014 Datasheet(PDF) 179 Page - Renesas Technology Corp

SH7014 Datasheet(HTML) 179 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL