SH7014 datasheet(303/754 Pages) RENESAS

303 / 754 page

10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 269 of 716

REJ09B0398-0500

10.7.9

Contention between TGR Write and Compare Match

If a compare-match occurs in the T

2 state of the TGR write cycle, data is written to the TGR and a

compare-match signal is issued (figure 10.56).

TGR

Compare

match signal

TCNT

Address

Write signal

TGR write cycle

TGR address

NN + 1

TGR write data

Figure 10.56 TGR Write and Compare Match Contention

10.7.10

TCNT2 Write and Overflow/Underflow Contention in Cascade Connection

With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs

during TCNT1 count (during a TCNT2 overflow/underflow) in the T

2 state of the TCNT2 write

cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if

there is match with TGR1A and the TCNT1 value, a compare signal is issued. Furthermore, when

the TCNT1 count clock is selected as the input capture source of channel 0, TGRA0 to TGRD0

carry out the input capture operation. In addition, when the compare match/input capture is

selected as the input capture source of TGRB1, TGRB1 carries out input capture operation. The

timing is shown in figure 10.57.

For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT

clearing.

SH7014 Datasheet(PDF) 303 Page - Renesas Technology Corp