SH7014 datasheet(306/754 Pages) RENESAS

306 / 754 page

10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 272 of 716

REJ09B0398-0500

10.7.12

Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and

overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is

not set .

Figure 10.59 shows the operation timing in this case.

Address

Write signal

TCNT input

clock

TCNT

TCFV flag

H'FFFF

TCNT write data

Disabled

TCNT write cycle

TCNT address

Figure 10.59 Contention between TCNT Write and Overflow

10.7.13

Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode 1

In PWM mode 1, the TGRA and TGRB registers are used in pairs and PWM waveform is output

to the TIOCA pin. In the same manner, the TGRC and TGRD registers are used in pairs and PWM

waveform is output to the TIOCC pin. If either the TGRC or TGRD register is operating as a

buffer register, the TIOCC pin cannot execute default output setting or PWM waveform output

with the I/O control register (TIOR).

Note that for channel 0, the TIOCC pin allows both default output setting by TIOR and PWM

output when setting buffer operation only for the TGRD register in PWM mode 1.

When using channel 0 in PWM mode 1 and setting buffer operation, use both the TGRC and

TGRD registers as buffer registers.

SH7014 Datasheet(PDF) 306 Page - Renesas Technology Corp