7641 datasheet(349/385 Pages) RENESAS

349 / 385 page

Rev.2.00

Aug 28, 2006

page 70 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

Fig. 3.5.37 Structure of DMAC channel x (x = 0, 1) mode register 1

DMAC channel x mode register 1 (x = 0, 1)

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel x mode register 1

(DMAxM1 : address 4016) (Note 1)

Name

Functions

At reset R W

0 : Increment after transfer

1 : Decrement after transfer

0 : Disabled (No change after transfer)

1 : Enabled

DMAC channel x source

selection bit (DxSRID)

DMAC channel x source

enable bit (DxSRCE)

0 : Increment after transfer

1 : Decrement after transfer

0 : Disabled (No change after transfer)

1 : Enabled

DMAC channel x destination

selection bit (DxDRID)

DMAC channel x destination

enable bit (DxDRCE)

DMAC channel x data

write control bit (DxDWC)

0 : Writing data in reload latches and

registers

1 : Writing data in reload latches only

DMAC channel x disable after

count register underflow

enable bit (DxDAUE)

0 : Channel x enabled after count

1 : Channel x disabled after count

DMAC channel x register

reload bit (DxRLD)

0 : Not reloaded

1 : Source, destination, and transfer

count registers contents of channel x

to be reloaded

DMAC channel x transfer

mode selection bit (DxTMS)

0 : Cycle steal transfer mode

1 : Burst transfer mode

(Note 2)

Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register

depends on channel index bit, bit 7 of DMAC index and status register.

2: These bits’ contents are “0” at read.

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