7641 datasheet(345/385 Pages) RENESAS

345 / 385 page

Rev.2.00

Aug 28, 2006

page 66 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

UARTx control register

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) control register

(UxCON : addresses 3316, 3B16)

Name

Functions

At reset R W

Receive enable bit (REN)

Transmit interrupt source

select bit (TIS)

CTS function enable bit

(CTS_SEL)

Receive initialization bit

(RIN)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

Transmit initialization bit

(TIN)

0 : No action

1 : Initializing (Note 1)

0 : No action

1 : Initializing (Note 2)

0 : CTS function disabled (Note 3)

1 : CTS function enabled

0 : Interrupt when transmit buffer has

emptied

1 : Interrupt when transmit shift operation

is completed

Transmit enable bit (TEN)

0 : RTS function disabled (Note 4)

1 : RTS function enabled

0 : Address mode disabled

1 : Address mode enabled

RTS function enable bit

(RTS_SEL)

UART address mode

enable bit (AME)

Notes 1: When setting the TIN bit to “1”, the TEN bit is set to “0” and the UARTx status

the TEN bit to “1” and set a data to the transmit buffer register again. The TIN bit

will be cleared to “0” one cycle later after the TIN bit has been set to “1”.

2: Setting the RIN bit to “1” suspends the receiving operation and will set all of the

REN, RBF and the receive error flags (PER, FER, OER, SER) to “0”. The RIN bit

will be cleared to “0” one cycle later after the RIN bit has been set to “1”.

3: When CTS function is disabled (CTS_SEl = “0”), pins P82 and P86 can be used as

ordinary I/O ports.

4: When RTS function is disabled (RTS_SEl = “0”), pins P83 and P87 can be used as

ordinary I/O ports.

Fig. 3.5.33 Structure of UARTx (x = 1, 2) control register

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