7641 datasheet(348/385 Pages) RENESAS

348 / 385 page

Rev.2.00

Aug 28, 2006

page 69 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

DMAC index and status register

b7 b6 b5 b4 b3 b2 b1 b0

DMAC index and status register

(DMAIS : address 3F16)

Name

Functions

At reset R W

DMAC channel 0 suspend

flag (D0SFI) (Note 1)

DMAC transfer suspend

control bit (DTSC) (Note 2)

DMAC channel 1 count

0 : No underflow

1 : Underflow generated

0 : Not suspended

1 : Suspended

DMAC channel 1 suspend

flag (D1SFI) (Note 1)

0 : No underflow

1 : Underflow generated

DMAC register reload

disable bit (DRLDD)

(Note 3)

Channel index bit (DCI)

0 : Channel 0 accessible

1 : Channel 1 accessible

Accessed registers: Mode register,

source register, destination register,

transfer count register.

DMAC channel 0 count

Fix this bit to “0”.

0 : Not suspended

1 : Suspended

0 :Suspending only burst transfers during

interrupt process

1 : Suspending both burst and cycle steal

transfers during interrupt process

0 :Enabling reload of source and

destination registers of both channels

1 : Disabling reload of source and

destination registers of both channels

Notes 1: Suspended by an interrupt.

2: Transfer suspended during interrupt process

3: This settings affect the source and destination registers of both channels.

✽

✽: “0” can be set by software, but “1” cannot be set.

Fig. 3.5.36 Structure of DMAC index and status register

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