7641 datasheet(346/385 Pages) RENESAS

346 / 385 page

Rev.2.00

Aug 28, 2006

page 67 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

UARTx transmit/receive buffer registers 1, 2

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) transmit/receive buffer register 1

(UxTRB1: addresses 3416, 3C16)

Undefined

Functions

At reset R W

Undefined

The transmit buffer register and the receive buffer register are located

at the same address. Writing a transmitting data and reading a

received data are performed through the UxTRB. This is its low-order

byte.

•At write

The data is written into the transmit buffer register. It is not done into

the receive buffer register.

•At read

The contents of receive buffer register is read.

If a character bit length is 7 bits, the MSB of received data is invalid.

Note that the contents of transmit buffer register cannot be read.

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) transmit/receive buffer register 2

(UxTRB2: addresses 3516, 3D16)

Undefined

Functions

At reset R W

Undefined

The transmit buffer register and the receive buffer register are located

at the same address. Writing a transmitting data and reading a

received data are performed through the UxTRB. This is its high-

order byte.

•At write

The data is written into the transmit buffer register. It is not done into

the receive buffer register.

•At read

The contents of receive buffer register is read.

If a character bit length is 9 bits, the received high-order 7 bits of

UxTRB2 are “0”

Note that the contents of transmit buffer register cannot be read. If a

character bit length is 7 or 8 bits, the received contents of UxTRB2

are invalid.

Nothing is arranged for this bit. This is a write disable bit. When this

bit is read out, the contents are “0”.

Fig. 3.5.34 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2

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