7641 datasheet(344/385 Pages) RENESAS

344 / 385 page

Rev.2.00

Aug 28, 2006

page 65 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

UARTx baud rate generator

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) baud rate generator

(UxBRG: addresses 3116, 3916)

Undefined

Functions

At reset R W

Undefined

qThe UxBRG determines the baud rate for transfer.

qThis is a 8-bit counter with its reload register. This generator divides

the frequency of the count source by 1/(n + 1), where “n” is the

value written to the UxBRG.

UARTx status register

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) status register

(UxSTS : addresses 3216, 3A16)

Name

Functions

At reset R W

Transmit buffer empty flag

(TBE)

Parity error flag (PER)

Framing error flag (FER)

Receive buffer full flag

(RBF)

0 : Transmit shift in progress

1 : Transmit shift completed

0 : Buffer full

1 : Buffer empty

0 : Buffer empty

1 : Buffer full

0 : No error

1 : Parity error

0 : No error

1 : Framing error

Overrun error flag (OER)

0 : No error

1 : Overrun error

Summing error flag (SER)

0 : (PER) U (FER) U (OER) = 0

1 : (PER) U (FER) U (OER) = 1

Transmit complete flag

(TCM)

Nothing is arranged for this bit. This is a write disable bit. When this

bit is read out, the contents are “0”.

Fig. 3.5.31 Structure of UARTx (x = 1, 2) baud rate generator

Fig. 3.5.32 Structure of UARTx (x = 1, 2) status register

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