7641 datasheet(343/385 Pages) RENESAS

343 / 385 page

Rev.2.00

Aug 28, 2006

page 64 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

Special count source mode register

b7 b6 b5 b4 b3 b2 b1 b0

Special count source mode register

(SCSGM : address 2F16)

Name

Functions

At reset R W

SCSG2 data write control

bit

SCSGCLK output control

bit

0 : Writing data into both timer latch and

timer simultaneously

1 : Writing data into timer latch

0 : Writing data into both timer latch and

timer simultaneously

1 : Writing data into timer latch

0 : SCSGCLK output disabled

(SCSG1 and SCSG2 counts stop)

1 : SCSGCLK output enabled

SCSG1 count stop bit

0 : Count start

1 : Count stop

SCSG1 data write control

bit

Fix these bits to “0”.

UARTx mode register

b7 b6 b5 b4 b3 b2 b1 b0

UARTx (x = 1, 2) mode register

(UxMOD : addresses 3016, 3816)

Name

Functions

At reset R W

UART clock prescaling

select bits (PS)

Parity select bit (PMD)

Parity enable bit (PEN)

Stop bit length select bit

(STB)

0 :

1 : SCSGCLK output

b2b1

0 0 : UART clock divided by 1

0 1 : UART clock divided by 8

1 0 : UART clock divided by 32

1 1 : UART clock divided by 256

0 : 1 stop bit

1 : 2 stop bits

0 : Even parity

1 : Odd parity

0 : Parity checking disabled

1 : Parity checking enabled

UART character length

select bit (LE1, 0)

UART clock select bit

(CLK)

b7b6

0 0 : 7 bits

0 1 : 8 bits

1 0 : 9 bits

1 1 : Not available

Fig. 3.5.29 Structure of Special count source mode register

Fig. 3.5.30 Structure of UARTx (x = 1, 2) mode register

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