7641 datasheet(167/385 Pages) RENESAS

167 / 385 page

Rev.2.00

Aug 28, 2006

page 36 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.2 Timer

Fig. 2.2.28 Control procedure

RESET

SEI

CCR

CPMA

TYM

P4D

TYL

TYH

IREQB

IREQC

ICONB

ICONC

TYM

CLI

XXX000002

000X10002

1101XXX02

FF16

(address 1F16)

(address 0016)

(address 2816)

(address 1916),bit4

(address 2216)

(address 2316)

(address 0316),bit5

(address 0416),bit2

(address 0616),bit5

(address 0716),bit2

(address 2816),bit7

RTI

•All interrupts disabled

Initialization

•Interrupts enabled

Main processing

Timer Y interrupt process routine

CLT (Note 1)

CLD (Note 2)

Push registers to stack

Pop registers

Notes 1: When using Index X mode flag (T)

2: When using Decimal mode flag (D)

q X: This bit is not used here. Set it to “0” or “1” arbitrary.

Phase control process

•Setting P44/CNTR1 pin to input mode

•Setting Timer X count value

(Set to the low-order and then high-order byte.)

•Clearing Timer Y interrupt request bit

•Clearing CNTR1 interrupt request bit

•Timer Y interrupt: Enabled

•CNTR1 interrupt: Enabled

•Timer Y count start

Error processing

RTI

CNTR1 interrupt process routine

CLT (Note 1)

CLD (Note 2)

Push registers to stack

Pop registers

Read Timer Y

(The high-order first and then low-order

byte)

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