7641 datasheet(164/385 Pages) RENESAS

164 / 385 page

Rev.2.00

Aug 28, 2006

page 33 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.2 Timer

Fig. 2.2.25 Control procedure (2)

RTI

(A)

Measurement result (high-order 8 bits)

(A)

Measurement result (low-order 8 bits)

TXL(address 2016)

TXH(address 2116)

TXH

(A)

TXL

(A)

FF16

FFFF16

000016

Count start of

Timer X

T1 value: Valid

CNTR0

FFFF16

000016

CNTR0

CNTR0 interrupt process routine

CLT (Note 1)

CLD (Note 2)

Push registers to stack

Pop registers

Notes 1: When using Index X mode flag (T)

2: When using Decimal mode flag (D)

•Pushing registers used in interrupt process routine

•Popping registers pushed to stack

•Count value read and storing it to RAM

Read the high-order and then low-order byte.

Write to the low-order and then high-order byte.

Note : The first value becomes invalid depending on start timing of Time X count shown

by the following figure.

Process it by software as necessary.

[ Example 1] • Start Timer X count when CNTR0 input level is “L”.

(CNTR0 input level can be checked by reading the contents of sharing port P43 register.

CNTR0 interrupt

T2 value: Valid

[ Example 2] • Start Timer X count when CNTR0 input level is “H”.

Invalidate the first CNTR0 interrupt after start of Timer X count.

Count start of

Timer X

T1 value: Invalid

T2 value: Valid

CNTR0 interrupt

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