7641 datasheet(163/385 Pages) RENESAS

163 / 385 page

Rev.2.00

Aug 28, 2006

page 32 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.2 Timer

Fig. 2.2.24 Control procedure (1)

(address 1716),bit7

(address 0016)

(address 1916),bit3

(address 2716)

(address 2016)

(address 2116)

(address 0616),bit4

(address 0316)

(address 0716),bit1

(address 0416)

(address 2716),bit7

RESET

SEI

CCR

CPMA

P4D

TXM

TXL

TXH

ICONB

IREQB

ICONC

IREQC

TXM

CLI

000X1XXX2

RTI

q X: This bit is not used here. Set it to “0” or “1” arbitrary.

•All interrupts disabled

Initialization

•Setting P43/CNTR0 pin to input mode

•Timer X: Pulse width measurement mode

(Measuring “H” pulse width of input pulses from CNTR0 pin)

•Setting Timer X count value

•Timer X interrupt: Enabled

•CNTR0 interrupt: Enabled

•Timer X count start

•Interrupts enabled

Timer X interrupt process routine (Note 1)

CLT (Note 2)

CLD (Note 3)

Push registers to stack

Error processing

Pop registers

Notes1: Timer X interrupt also occurs owing to factors other than

measurement level.(CNTR2 input = “L” in this application)

Process it by software as error proccesing is performed for

measurement level as necessary . CNTR2 input level can be

checked by reading the contents of sharing port P83 register.

2: When using Index X mode flag (T)

3: When using Decimal mode flag (D)

•Popping registers pushed to stack

•Pushing registers used in interrupt process routine

101101102

FF16

000000002

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